Fascinating panel discussion at #DAC about RISC-V verification challenges, as reported by the Daniel Nenni at Semiwiki: Industry leaders highlighted how the rapid adoption of #RISCV creates new verification complexities, particularly around custom instructions and security.
As panelist Ty Garibay (Condor) noted, while RISC-V’s extensibility is one of its greatest strengths, it brings additional verification responsibilities. Josh Scheid (Ventana Microsystems) emphasized that “the verification bar is high, complex and focused on certain verticals.”
At Veriest, we’ve been ahead of this curve. Our extensive experience in formal verification has proven invaluable for RISC-V projects, especially when dealing with custom instruction extensions. As the panel discussed, formal methods are particularly crucial for:
· Validating security properties
· Proving state combinations that are difficult to reach through simulation
· Ensuring custom instructions don’t break existing functionality
· C-to-RTL equivalence checking for instruction extensions
The panelists’ observation about RISC-V’s spec needing better formal-friendly representation resonates with our experience. We’ve developed ways to bridge this gap, helping our clients achieve robust verification coverage while accelerating their time to market.
Looking to extend RISC-V cores or ensure your custom instructions are thoroughly verified?
Let’s discuss how Veriest’s expertise can help secure your design’s success.
full article: https://semiwiki.com/eda/siemens-eda/350050-changing-risc-v-verification-requirements-standardization-infrastructure/