Djordje Velickovic and Milos Pericic, Verification Engineers at Veriest have authored a paper that was presented at DVCON Europe 2022.
Abstract— This paper intends to present the advantages of modelling standard UVC monitor class for packet-based interface as a finite state machine. It will do so by explaining in depth, the concept of UVC monitor class using the FSM model on an open-source Ethernet core IP TX interface. It compares it to a traditionally coded monitor class with emphasis on the advantages of the proposed solution in debugging such interface and coding of protocol violation checkers. It also shows that all these advantages are achieved without adding degradation in CPU usage percentage and simulation time.
Modelling of UVC Monitor Class as a Finite State Machine for a Packet-Based Interface