Milos Pericic, Senior Verification Engineer at Veriest’s New Belgrade office,
has authored a paper on SystemVerilog constraints optimization that was presented at DVCon Europe 2024.
Abstract – Constraints in SystemVerilog language are useful for randomization. When there are connections between randomized variables, then constraints could be used for randomizing everything together. In a larger project, the number of connections can grow and expand, resulting in complex randomized test scenarios. In those cases, constraints should be written as good as possible, and their performance should be tested. In this paper, a few useful techniques will be covered for improving performance of constraints.
The paper addresses critical challenges in managing complex constraint systems within large-scale verification projects. As modern chip designs grow in complexity, efficient constraint handling becomes increasingly crucial for effective randomization and test scenario generation.