This Veriest Solutions presentation from Cadence Live Israel 2019 demonstrates formal verification methodologies for a custom microcontroller design. It covers verification challenges in pipelined architectures and presents solutions for comparing execution results with golden reference models. The approach successfully verified 85 of 94 assembler instructions, identifying various bug types and proving that microcontroller designs are well-suited for formal verification techniques.
Automated Configuration of Verification Environments using Specman Macros
Purim Party 2019