Chiplet technology represents a paradigm shift in semiconductor design, heralding a new era of more modular and efficient approach to building complex systems-on-chip (SoCs). As European and U.S. companies embrace chiplet strategies to overcome Moore’s Law limitations and continue boosting performance, a critical aspect often overlooked is the necessary evolution of verification methodologies to meet the interfacing requirements of complex chiplet structures.
At DVCon Europe 2023, Veriest CEO Moshe Zalcberg joined the panel “The Great Verification Chiplet Challenge” alongside executives from Nokia, IBM, Axiomise, and Breker Verification Systems. Moderated by Nick Flaherty, Editor-in-Chief of eeNews Europe, this discussion explored the verification challenges facing the industry as it adopts chiplet technology and the UCIe interconnect standard.
The panel addressed why verification must expand beyond traditional functional block tests and explored comprehensive strategies including simulation, emulation, and hardware/software co-verification to ensure reliability and functionality of chiplet-based systems.