This paper was written by Francesco Rua’, ST Microelectronics and Péter Sági, Verification Engineers at Veriest, and presented at DVCon Europe 2023.
Abstract— AXI protocol high-performance features and cache performance requirements demand a careful strategy for verification to be decided in advance. This is very important to achieve the main targets: minimum effort for development and maintenance of the testbench; minimum dependency on DUT microarchitecture; effective debug strategy.
A high-performance cache controller employs intense pipelining as a significant part of its microarchitecture. Such a microarchitecture may be deeply changed for either new functionality, further improvements or bug fixes, and a well-designed testbench should not be affected heavily by those changes. Pipelining inside a cache controller also implies parallel accesses to both cache and external memories from different stages of the pipeline(s), and every access may affect the next stages as well. Therefore, a design defect could be difficult to analyze if we base our debug on mere data integrity checks.
An effective testbench for a cache controller and, in general, for pipelined designs should be abstract as much as possible in order to treat DUT’s microarchitecture as a black box. The testbench can still get synchronized with the DUT behavior by means of observed transactions on its interfaces. It should also use point to point scoreboards at each DUT interface, so that the very first error will show the way to its root cause. In this paper we describe our approach based on well-known OOP design patterns, point to point scoreboards and multithreading.
Verification of an AXI cache controller with a multi-thread approach based on OOP design patterns