Attending DVCon Europe 2024 was an exciting and fulfilling experience, especially since it marked
another opportunity for me to present work in the field of functional verification. As someone who
has had the chance to present at various conferences before, I can confidently say that each
experience brings something new—whether it’s refining your approach, engaging with a different
audience, or making meaningful connections with industry peers. This year’s event was no
exception.
DVCon Europe is one of the premier conferences within Europe for professionals in the ASIC and
semiconductor space, and it’s always a privilege to be part of such a prestigious event. The
conference brings together design and verification specialists from across the globe to share
insights, discuss the latest trends, and address the challenges in the ever-evolving world of ASIC
development. Having been to this conference before, I was eager to return and present the results
of my recent project to an audience of experts who are equally passionate about the technical
intricacies of verification process for hardware design.
The experience of presenting at a conference like DVCon is unique in its own right. As I stood before
the audience talking about comparative case study we developed to show performance differences
between usage of C model in verification through DPIC function and using static pre generated value
tables, I could tell that were more than interested in the theoretical aspects of different C model
integration approaches we used, as well as in practical performance measurements that paper
showcases. The discussions that followed my presentation were engaging and stimulating, with
questions and feedback from both industry veterans and more junior verification enthusiasts. It’s
incredibly rewarding to receive input from fellow verification engineers and see how they are invested
in questions we tried to answer through our paper. One of the highlights of the session was a
discussion on broader usage of C models in functional verification and limitations to this approach.
In addition to presenting my own work, the conference offered invaluable networking opportunities.
I had the chance to connect with engineers and leaders from different companies, exchanging
insights into the tools and methodologies shaping the future of ASIC design. It’s one of those
opportunities where you can talk with people who are tackling major challenges of the
semiconductor industry, and the connections you make might lead to future collaborations.
What I especially appreciate about DVCon Europe is the focus on practical, actionable knowledge.
It’s not just about sharing research findings. it’s about learning from each other and collectively
advancing the field. Whether you’re discussing the latest in simulation tools, verification
methodologies, or new trends in design automation, the sessions are rich with knowledge that can
be immediately applied to your own work.
Looking back on the conference, I’m grateful for the opportunity to share my insights with such a
knowledgeable audience and to engage in conversations that are pushing existing methodologies
and verification practices forward. It was a reminder of how powerful it is to be part of an industry
that was built on collaboration and innovation. As I reflect on the discussions and feedback from
DVCon Europe 2024, I’m already looking forward to next year’s conference